The ultra-low jitter clock allocation solution incorporates EZSync multi-chip synchronization

     Linear Technology Corporation introduces the LTC6954, a series of ultra-low jitter 1.8GHz clock distribution chips with three separate outputs, each with its own divider and phase delay. With an additional jitter of less than 20fsRMS over a bandwidth of 12kHz to 20 MHZ, the LTC6954 divides and distributes the input clock while minimizing introduced noise. This enables the LTC6954 to provide a clock with very low jitter, which is necessary to achieve the best signal-to-noise ratio (SNR) when driving high-resolution data converters. For example, low jitter ADC clocks are especially important when digitizing RF or high IF high frequency analog signals, making the LTC6954 an ideal clock solution in such systems.

     The LTC6954 family includes four versions of the device, offering a variety of different combinations of LVPECL and LVDS/CMOS output logic drivers. This allows the flexibility to optimally connect to a large number of devices that receive different logic signals. Powered by a single 3.3V supply, the LTC6954 is set by SPI to independently split the input clock at any integer in the range of 1 to 63, and is capable of independently delaying each output with 0 to 63 input clock cycles. This makes it easy to build the necessary phase-shift clocks, for example, ADCs that drive the I and Q channels in a communication system.

     In addition to being able to be used as a standalone clock distributor, the LTC6954 also uses Linear Technology's proprietary EZSync™ synchronization method. EZSync synchronization is triggered by a simple pulse that aligns multiple outputs from one or more chips with the rising edge to produce a repeatable and deterministic phase relationship between all clock divider outputs. The LTC6954 can be paired with the LTC6950 as a follower to increase the amount of low-jitter edge alignment clock output generated by the LTC6950.