Silicon Labs reduces the cost and complexity of timing technology for the coherent light market

     Silicon Labs has introduced a series of jitter attenuating clocks that simplify 100G/400G Coherent Optical Line Card and module design, significantly reducing system cost and complexity by providing a high frequency, flexible clock solution. Silicon Labs' new Si534xH coherent optical clock provides low-jitter reference timing for data converters as an alternative to discrete timing solutions that rely on expensive, large-package size volt-controlled SAW oscillators (VCSO). Unlike VCSO, which only supports a single fixed frequency, the new Si534xH clock offers a wide frequency range, supporting frequencies up to 2.7GHz without changing Bill of Materials (BOM) components.

     The Si5344H and Si5342H clocks offer optimal frequency flexibility and unmatched 50fs RMS jitter performance. These clock chips simplify the device procurement process and allow a single clock IC solution with lead times as short as two weeks to replace multiple customized VCsos with long lead times. With jitter attenuation PLL, high frequency output driver, fractional frequency synthesis and digital controlled oscillator (DCO) technology, the Si534xH family provides all the clock functionality needed for coherent optical transceiver applications with 40% less footprint and 40% less power consumption than competing solutions.

     One of the biggest growth drivers in the communications market is the shift from 10G to 100G in the area of metropolitan networks and data center Interconnectivity (DCI) in the industry. Coherent optics technology can be used for 100G and 400G applications because it enables service providers to send more data over existing fibers, reducing the cost and complexity of network upgrades for bandwidth expansion. Current timing solutions for coherent light are not yet optimized in terms of cost and size and require a diverse combination of VCsos, clock generators and discrete devices.

     Silicon Labs' Si534xH clock is specifically designed to meet the timing requirements of 100G/400G coherent light applications. In addition to supporting the UHF synthesis required for timing in optical transceiver data converters, the Si534xH clock incorporates Silicon Labs' market-proven DSPLL jitter attenuation technology and MultiSynth low jitter fraction frequency synthesis technology to provide a smart, easy-to-use single-chip solution. All 100G/400G transmitter or receiver clocks can be generated from a single chip, minimizing BOM costs and reducing complexity by eliminating a large number of discrete components.

     James Wilson, senior marketing Director of Timing products at Silicon Labs, said: "To meet increasing bandwidth demands, operators need  100G/400G coherent designs to achieve higher line card port densities and lower bit costs than traditional solutions. "Silicon Labs' Si534xH clock products offer significantly reduced footprint and lower power consumption compared to traditional VCSO-based solutions, providing the high frequency clock synthesis, jitter attenuation and stringent phase noise required for coherent light applications."

     Coherent clock development is supported by Silicon Labs' ClockBuilder TM, an easy-to-use software tool that simplifies clock tree design, device configuration, and evaluation of detailed performance. The tool can generate the chip profile independently or directly control the Si534xH chip on the evaluation board. ClockBuilder Pro can also be used to create factory customized versions of Silicon Labs jitter attenuators and clock generators to meet each customer's unique timing requirements.