Lattice further enriches CrossLink applications by providing modular IP cores

Lattice Semiconductor, a leading provider of customized intelligent interconnect solutions to the market, announced the launch of seven new modular IP cores that support the award-winning CrossLink FPGA product family, providing increased design flexibility for consumer electronics, industrial and automotive applications. These modular IP cores provide customers with the building blocks needed to create custom video bridging solutions.

In the mobile industry, the need for high-volume and high-performance components has driven a variety of video components to the market, such as processors, displays and sensors, which are also popular in other "mobile-related" markets. These markets require cost-effective devices that bridge solutions between MIPI and other traditional or existing display and camera interfaces.

"Our customers need FPgas with MIPI D-PHY to solve the growing video interface problem." Tom Watzka, product marketing manager at Lattice Semiconductor, said, "They often encounter obstacles in terms of power consumption, size and performance. For more than a year, Lattice CrossLink devices and their family of IP cores have been helping design engineers overcome these challenges. The addition of these new ips to an already robust suite of tools further enhances support for the rapidly evolving intelligence applications at the network edge."

The CrossLink product, which went on sale in May 2016, is designed to address the challenges of an increasingly complex and fast-changing video market. Lattice offers design engineers a new way to achieve low power and small bridging solutions without compromising performance, providing cutting-edge innovation for several fast-growing markets including automotive, AR/VR and drones.

The new CrossLink modular IP core includes:

● CSI-2/DSI D-PHY receiver - Converts MIPI CSI-2/DSI data streams into parallel data

● CSI-2/DSI D-PHY transmitter - Converts parallel format data streams to MIPI CSI-2/DSI format

● FPD-LINK receiver - Converts the FPD-LINK video stream into the pixel clock domain

● FPD-LINK transmitter - converts the pixel data stream into an FPD-LINK video stream

● SubLVDS image Sensor receiver - Converts SubLVDS image sensor video data into pixel clock domains

● Pixel-to-byte data conversion - Converts D-PHY transmitter pixel format data to parallel data format

● Byte data to pixel conversion - Converts parallel data from the D-PHY receiver to pixel format

In addition, Lattice introduced the 1:2 MIPI DSI Display interface bandwidth Reducer, which utilizes the aforementioned modular IP core to bridge input video streams into two video streams or one lower resolution video stream.