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Cypress Low Pin Count HyperRAM™ memory simplifies the design of embedded systems

dic 12 2016 2016-12 Semiconductors Cypress Semiconductor
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Cypress Semiconductor, a leader in embedded system solutions, announced that its new high-speed self-refreshing dynamic RAM(DRAM) based on the low-pin HyperBus interface is now available for demo. The 64Mb HyperRAM™ can be used as an external notepad memory for a wide range of automotive, industrial and consumer applications to render high-resolution graphics or run data-intensive firmware algorithms. The device has a read/write bandwidth of up to 333 MBps and supports 3V and 1.8V supply voltages.

     Cypress Semiconductor, a leader in embedded system solutions, announced that its new high-speed self-refreshing dynamic RAM(DRAM) based on the low-pin HyperBus interface is now available for demo. The 64Mb HyperRAM™ can be used as an external notepad memory for a wide range of automotive, industrial and consumer applications to render high-resolution graphics or run data-intensive firmware algorithms. The device has a read/write bandwidth of up to 333 MBps and supports 3V and 1.8V supply voltages.

     When used in conjunction with Cypress's HyperFlash™ NOR flash memory, HyperRAM provides a simple, cost-effective solution for embedded systems by allowing flash and RAM to share the same 12-pin HyperBus. Traditional systems with SDRAM and Dual-Quad SPI solutions require 41 upstream pins on two buses to process data; HyperRAM and HyperFlash solutions reduce the number of pins by at least 28, simplifying designs and reducing PCB costs. HyperRAM is the ideal solution for automotive dashboards and infotainment systems, communications devices, industrial applications and high performance consumer electronics.

     Rainer Hoehler, vice president of Cypress Flash, said: "As high-resolution graphics and data-intensive applications become increasingly common in all types of systems, there is a growing demand for simple, high-performance DRAM that can provide external notepad memory for controllers with limited on-board RAM. With the low-pin HyperBus interface and its industry-leading read/write bandwidth, our new 64Mb HyperRAM will meet this demand. In addition to reducing the cost of PCBS, HyperRAM also reduces the cost of MCUS by reducing the number of pins compared to other DRAM solutions."

     To speed up product development, Cypress offers the HyperBus master device Interface Controller IP to customers and partners. This controller IP helps designers add support for HyperBus to their field programmable gate array (FPGA), application-specific integrated circuit (ASIC), or application-specific Standard Product (ASSP) host control platform.

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